//BEGIN ADC INSTRUCTION *****************************************************
//All ADC variations are supported, except the useless repeats.
{adc}
//First entry is for optimization.
eax_ax_al,byte = 1000 00<s><w> : 11 010 000 : <byte>|
eax_ax_al,imm = 0001 010<w> : <imm>|
reg,imm = 1000 00<s><w> : 11 010 <regdest> : <imm>|
reg,reg = 0001 000<w> : 11 <regsrc> <regdest>|
reg,mem = 0001 001<w> : <mod> <regdest> <r/m>|
mem,reg = 0001 000<w> : <mod> <regsrc> <r/m>|
mem,imm = 1000 00<s><w> : <mod> 010 <r/m> : <imm>
{/adc}

//BEGIN ADD INSTRUCTION *****************************************************
//All ADD variations are supported, except the useless repeats.
{add}
//First entry is for optimization.
eax_ax_al,byte = 1000 00<s><w> : 11 000 000 : <byte>|
eax_ax_al,imm = 0000 010<w> : <imm>|
reg,imm = 1000 00<s><w> : 11 000 <regdest> : <imm>|

reg,reg = 0000 000<w> : 11 <regsrc> <regdest>|
reg,mem = 0000 001<w> : <mod> <regdest> <r/m>|
mem,reg = 0000 000<w> : <mod> <regsrc> <r/m>|
mem,imm = 1000 00<s><w> : <mod> 000 <r/m> : <imm>
{/add}

//BEGIN AND INSTRUCTION *****************************************************
//(All variations supported)
{and}
eax_ax_al,imm = 0010 010<w> : <imm>|
reg,reg = 0010 000<w> : 11 <regsrc><regdest>|
reg,mem = 0010 001<w> : <mod> <regdest> <r/m>|
mem,reg = 0010 000<w> : <mod> <regsrc> <r/m>|
reg,imm = 1000 00<s><w> : 11 100 <regdest> : <imm>|
mem,imm = 1000 00<s><w> : <mod> 100 <r/m> : <imm>
{/and}

//BEGIN ARPL INSTRUCTION *****************************************************
//(All variations supported)
{arpl}
reg16,reg16 = 0110 0011 : 11 <regsrc> <regdest>|
memword,reg16 = 0110 0011 : <mod> <regsrc> <r/m>
{/arpl}

//BEGIN BOUND INSTRUCTION *****************************************************
//(All variations supported)
{bound}
reg32,mem = 0110 0010 : <mod> <regdest> <r/m>|
reg16,mem = 0110 0010 : <mod> <regdest> <r/m>
{/bound}

//BEGIN BSF INSTRUCTION *****************************************************
//(All variations supported)
{bsf}
reg32,reg32 = 0000 1111 : 1011 1100 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111 : 1011 1100 : 11 <regdest> <regsrc>|
reg16,memword = 0000 1111 : 1011 1100 : <mod> <regdest> <r/m>|
reg32,mem = 0000 1111 : 1011 1100 : <mod> <regdest> <r/m>
{/bsf}

//BEGIN BSR INSTRUCTION *****************************************************
//(All variations supported)
{bsr}
reg32,reg32 = 0000 1111 : 1011 1101 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111 : 1011 1101 : 11 <regdest> <regsrc>|
reg16,memword = 0000 1111 : 1011 1101 : <mod> <regdest> <r/m>|
reg32,mem = 0000 1111 : 1011 1101 : <mod> <regdest> <r/m>
{/bsr}

//BEGIN BSWAP INSTRUCTION *****************************************************
//(All variations supported)
{bswap}
reg32 = 0000 1111 : 1100 1 <regdest>
{/bswap}

//BEGIN BT INSTRUCTION *****************************************************
//(All variations supported)
{bt}
memword,reg16 = 0000 1111 : 1010 0011 : <mod> <regsrc> <r/m>|
mem,reg32 = 0000 1111 : 1010 0011 : <mod> <regsrc> <r/m>|
reg32,byte = 0000 1111 : 1011 1010 : 11 100 <regdest>: <byte>|
reg16,byte = 0000 1111 : 1011 1010 : 11 100 <regdest>: <byte>|
mem,byte = 0000 1111 : 1011 1010 : <mod> 100 <r/m> : <byte>|
reg32,reg32 = 0000 1111 : 1010 0011 : 11 <regsrc> <regdest>|
reg16,reg16 = 0000 1111 : 1010 0011 : 11 <regsrc> <regdest>
{/bt}

//BEGIN BTC INSTRUCTION *****************************************************
//(All variations supported)
{btc}
memword,reg16 = 0000 1111 : 1011 1011 : <mod> <regsrc> <r/m>|
mem,reg32 = 0000 1111 : 1011 1011 : <mod> <regsrc> <r/m>|
reg32,byte = 0000 1111 : 1011 1010 : 11 111 <regdest>: <byte>|
reg16,byte = 0000 1111 : 1011 1010 : 11 111 <regdest>: <byte>|
mem,byte = 0000 1111 : 1011 1010 : <mod> 111 <r/m> : <byte>|
reg32,reg32 = 0000 1111 : 1011 1011 : 11 <regsrc> <regdest>|
reg16,reg16 = 0000 1111 : 1011 1011 : 11 <regsrc> <regdest>
{/btc}

//BEGIN BTR INSTRUCTION *****************************************************
//(All variations supported)
{btr}
memword,reg16 = 0000 1111 : 1011 0011 : <mod> <regsrc> <r/m>|
mem,reg32 = 0000 1111 : 1011 0011 : <mod> <regsrc> <r/m>|
reg32,byte = 0000 1111 : 1011 1010 : 11 110 <regdest>: <byte>|
reg16,byte = 0000 1111 : 1011 1010 : 11 110 <regdest>: <byte>|
mem,byte = 0000 1111 : 1011 1010 : <mod> 110 <r/m> : <byte>|
reg32,reg32 = 0000 1111 : 1011 0011 : 11 <regsrc> <regdest>|
reg16,reg16 = 0000 1111 : 1011 0011 : 11 <regsrc> <regdest>
{/btr}

//BEGIN BTS INSTRUCTION *****************************************************
//(All variations supported)
{bts}
memword,reg16 = 0000 1111 : 1010 1011 : <mod> <regsrc> <r/m>|
mem,reg32 = 0000 1111 : 1010 1011 : <mod> <regsrc> <r/m>|
reg32,byte = 0000 1111 : 1011 1010 : 11 101 <regdest>: <byte>|
reg16,byte = 0000 1111 : 1011 1010 : 11 101 <regdest>: <byte>|
mem,byte = 0000 1111 : 1011 1010 : <mod> 101 <r/m> : <byte>|
reg32,reg32 = 0000 1111 : 1010 1011 : 11 <regsrc> <regdest>|
reg16,reg16 = 0000 1111 : 1010 1011 : 11 <regsrc> <regdest>
{/bts}

//BEGIN CALL INSTRUCTION *****************************************************
//(All variations supported)
{call}
reldisp = 1110 1000 : <reldisp>|
reg = 1111 1111 : 11 010 <regdest>|
mem = 1111 1111 : <mod> 010 <r/m>
{/call}

//BEGIN CMP INSTRUCTION ****************************************************
//All CMP variations are supported, except the useless repeats.
{cmp}
//Special version of entry X for optimization purposes.
eax_ax_al,byte = 1000 00<s><w> : 11 111 000 : <byte>|
eax_ax_al,imm = 0011 110<w> : <imm>|
reg,reg = 0011 100<w> : 11 <regsrc><regdest>|
mem,reg = 0011 100<w> : <mod><regsrc><r/m>|
reg,mem = 0011 101<w> : <mod><regdest><r/m>|
reg,imm = 1000 00<s><w> : 11 111 <regdest> : <imm>| //Entry X.
mem,imm = 1000 00<s><w> : <mod> 111 <r/m> : <imm>
{/cmp}

//BEGIN CMPXCHG INSTRUCTION *****************************************************
//(All variations supported)
{cmpxchg}
reg,reg = 0000 1111 : 1011 000<w> : 11 <regsrc> <regdest>|
mem,reg = 0000 1111 : 1011 000<w> : <mod> <regsrc> <r/m>
{/cmpxchg}

//BEGIN CMPXCHG8B INSTRUCTION *****************************************************
//(More than all variations supported)
{cmpxchg8b}
//Note: For this variation, Intel says the last part is <regdest>, but OllyDbg
//implies that it can only be 001.
//Also, this is one of the few instructions that takes a QWORD sized memory operand.
mem = 0000 1111 : 1100 0111 : <mod> 001 <r/m>|
//Note: the second variation is not supported by Intel or OllyDbg!
//It's here because of a joke. The F00F joke.
reg = 0000 1111 : 1100 0111 : 11 001 <regdest>
{/cmpxchg8b}

//BEGIN DEC INSTRUCTION *****************************************************
//All DEC variations are supported, except the useless repeats.
{dec}
//Bytes only.
reg8 = 1111 1110 : 11 001 <regdest>|
//Dwords and Words only.
reg = 0100 1 <regdest>|
mem = 1111 111<w> : <mod> 001 <r/m>
{/dec}

//BEGIN DIV INSTRUCTION *****************************************************
//(All variations supported)
{div}
reg = 1111 011<w> : 11 110 <regdest>|
mem = 1 011<w> : <mod> 110 <r/m>
{/div}

//BEGIN ENTER INSTRUCTION *****************************************************
//(All variations supported)
{enter}
word,byte = 1100 1000 : <word> : <byte>
{/enter}

//BEGIN IDIV INSTRUCTION *****************************************************
//(All variations supported)
{idiv}
reg = 1111 011<w> : 11 111 <regdest>|
mem = 1 011<w> : <mod> 111 <r/m>
{/idiv}

//BEGIN IMUL INSTRUCTION *****************************************************
//All IMUL variations are supported, except the useless repeats.
{imul}
//Aliases for IMUL <whatever>,eax (same thing as IMUL <whatever> -- EAX is implied.)
reg = 1111 011<w> : 11 101 <regdest>|
mem = 1111 011<w> : <mod> 101 <r/m>|

//Do NOT use these two variations.
//IMUL EAX and IMUL EAX,EAX do different things.
//the first stores to EDX:EAX and the second to EAX.
//eax_ax_al,reg = 1111 011<w> : 11 101 <regdest>|
//eax_ax_al,mem = 1111 011<w> : <mod> 101 <r/m>|

reg,reg = 0000 1111 : 1010 1111 : 11 <regdest> <regsrc>|
reg,mem = 0000 1111 : 1010 1111 : <mod> <regdest> <r/m>|

//For IMUL, it's always regdest, then regsrc.
reg,reg,imm = 0110 10<s>1 : 11 <regdest><regsrc> : <imm>|
reg,mem,imm = 0110 10<s>1 : <mod> <regdest> <r/m> : <imm>
{/imul}

//BEGIN IN INSTRUCTION *****************************************************
//NOT ALL IN variations are supported!
//IN AX,DX
//IN EAX,DX  <--Yes, different sized operands!
//And perhaps others.
//This shouldn't really matter since modern OSes don't let you use IN.
//You can use variable-port IN as a substitute for STOSD in your unsupported
//tutorial.
{in}
eax_ax_al,byte = 1110 010<w> : <byte>
{/in}

//BEGIN INC INSTRUCTION *****************************************************
//All INC variations are supported, except the useless repeats.
{inc}
//Invented a new type: reg8.
reg8 = 1111 1110 : 11 000 <regdest>| /*Use type "reg8". The last bit of the 1st byte is supposed to be
                                       <w>, not 0, but since this will always take an 8-bit register,
									   we save time by not including the <w> field*/
//Optimized for dwords and words ONLY. Does not accept byte-registers (see above entry)
reg = 0100 0 <regdest>|
mem = 1111 111<w> : <mod> 000 <r/m>
{/inc}

//BEGIN INT INSTRUCTION *****************************************************
//(All variations supported)
{int}
byte = 1100 1101 : <byte>
{/int}

//BEGIN INVLPG INSTRUCTION *****************************************************
//(All variations supported)
{invlpg}
mem = 0000 1111 : 0000 0001 : <mod> 111 <r/m>
{/invlpg}

//BEGIN LAR INSTRUCTION *****************************************************
//(All variations supported)
{lar}
reg16,memword = 0000 1111 : 0000 0010 : <mod> <regdest> <r/m>|
reg32,reg32 = 0000 1111 : 0000 0010 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111 : 0000 0010 : <mod> <regdest> <r/m>|
reg16,reg16 = 0000 1111 : 0000 0010 : 11 <regdest> <regsrc>
{/lar}

//BEGIN L(segment register) INSTRUCTIONs *****************************************************
//(All variations supported)
{lds}
reg32,mem = 1100 0101 : <mod> <regdest> <r/m>
{/lds}

{les}
reg32,mem = 1100 0100 : <mod> <regdest> <r/m>
{/les}

{lfs}
reg32,mem = 0000 1111 : 1011 0100 : <mod> <regdest> <r/m>
{/lfs}

{lgs}
reg32,mem = 0000 1111 : 1011 0101 : <mod> <regdest> <r/m>
{/lgs}

{lss}
reg32,mem = 0000 1111 : 1011 0010 : <mod> <regdest> <r/m>
{/lss}
//END L(segment register) INSTRUCTIONs *****************************************************

//BEGIN LEA INSTRUCTION *****************************************************
//(All variations supported - yes there's only one.)
{lea}
reg,mem = 1000 1101 : <mod> <regdest> <r/m>
{/lea}

//BEGIN LGDT INSTRUCTION *****************************************************
//(All variations supported)
{lgdt}
mem = 0000 1111 : 0000 0001 : <mod> 010 <r/m>
{/lgdt}

//BEGIN LIDT INSTRUCTION *****************************************************
//(All variations supported)
{lidt}
mem = 0000 1111 : 0000 0001 : <mod> 011 <r/m>
{/lidt}

//BEGIN LLDT INSTRUCTION *****************************************************
//(All variations supported)
{lldt}
reg16 = 0000 1111 : 0000 0000 : 11 010 <regdest> |
memword = 0000 1111 : 0000 0000 : <mod> 010 <r/m>
{/lldt}

//BEGIN LMSW INSTRUCTION *****************************************************
//(All variations supported)
{lmsw}
reg16 = 0000 1111 : 0000 0001 : 11 110 <regdest> |
memword = 0000 1111 : 0000 0001 : <mod> 110 <r/m>
{/lmsw}

//BEGIN LSL INSTRUCTION *****************************************************
//(All variations supported)
{lsl}
reg32,reg32 = 0000 1111 : 0000 0011 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111 : 0000 0011 : 11 <regdest> <regsrc>|
reg16,memword = 0000 1111 : 0000 0011 : <mod> <regdest> <r/m>|
reg32,mem = 0000 1111 : 0000 0011 : <mod> <regdest> <r/m>
{/lsl}

//BEGIN LTR INSTRUCTION *****************************************************
//(All variations supported)
{ltr}
reg16 = 0000 1111 : 0000 0000 : 11 011 <regdest>|
memword = 0000 1111 : 0000 0000 : <mod> 011 <r/m>
{/ltr}

//BEGIN MOV INSTRUCTION ****************************************************
//All MOV variations are supported, except the useless repeats.
{mov}
eax_ax_al,memdisp = 1010 000<w> : <memdisp>|
memdisp,eax_ax_al = 1010 001<w> : <memdisp>|
reg,reg = 1000 100<w> : 11 <regsrc><regdest>|
reg,mem = 1000 101<w> : <mod><regdest><r/m>|
mem,reg = 1000 100<w> : <mod><regsrc><r/m>|

/*Before inserting an immediate data chunk at the end of
an instruction, search for the <imm> field.
If there's no field, then just append the immediate data
to the end.*/

//OR, just use your method of searching for fields only, then replacing them.
reg,imm = 1011 <w><regdest> : <imm>|

//Do NOT put a pipe on the last statement before the closing tag.
mem,imm = 1100 011<w> : <mod>000<r/m> : <imm>
{/mov}

//BEGIN MOVSX INSTRUCTION ***************************************************
//(All variations supported)
{movsx}
reg32,reg16 = 0000 1111 : 1011 1111 : 11 <regdest> <regsrc>|
reg32,reg8 = 0000 1111 : 1011 1110 : 11 <regdest> <regsrc>|
reg16,reg8 = 0000 1111 : 1011 1110 : 11 <regdest> <regsrc>|
reg32,memword = 0000 1111 : 1011 1111 : <mod> <regdest> <r/m>|
reg32,membyte = 0000 1111 : 1011 1110 : <mod> <regdest> <r/m>|
reg16,membyte = 0000 1111 : 1011 1110 : <mod> <regdest> <r/m>
{/movsx}

//BEGIN MOVZX INSTRUCTION ***************************************************
//(All variations supported)
{movzx}
reg32,reg16 = 0000 1111 : 1011 0111 : 11 <regdest> <regsrc>|
reg32,reg8 = 0000 1111 : 1011 0110 : 11 <regdest> <regsrc>|
reg16,reg8 = 0000 1111 : 1011 0110 : 11 <regdest> <regsrc>|
reg32,memword = 0000 1111 : 1011 0111 : <mod> <regdest> <r/m>|
reg32,membyte = 0000 1111 : 1011 0110 : <mod> <regdest> <r/m>|
reg16,membyte = 0000 1111 : 1011 0110 : <mod> <regdest> <r/m>
{/movzx}

//BEGIN MUL INSTRUCTION ***************************************************
//(All variations supported)
{mul}
reg = 1111 011<w> : 11 100 <regdest>|
mem = 1111 011<w> : <mod> 100 <r/m>
{/mul}

//BEGIN NEG INSTRUCTION *****************************************************
//(All variations supported)
{neg}
reg = 1111 011<w> : 11 011 <regdest>|
mem = 1111 011<w> : <mod> 011 <r/m>
{/neg}

//BEGIN NOT INSTRUCTION *****************************************************
//(All variations supported)
{not}
reg = 1111 011w : 11 010 <regdest>|
mem = 1111 011w : <mod> 010 <r/m>
{/not}

//BEGIN OR INSTRUCTION *****************************************************
//(All variations supported)
{or}
eax_ax_al,imm = 0000 110<w> : <imm>|
reg,reg = 0000 100<w> : 11 <regsrc><regdest>|
reg,mem = 0000 101<w> : <mod> <regdest> <r/m>|
mem,reg = 0000 100<w> : <mod> <regsrc> <r/m>|
reg,imm = 1000 00<s><w> : 11 001 <regdest> : <imm>|
mem,imm = 1000 00<s><w> : <mod> 001 <r/m> : <imm>
{/or}

//BEGIN OUT INSTRUCTION ***************************************************
//(Not all variations supported, see IN for more details)
{out}
byte,eax_ax_al = 1110 011<w> : <byte>
{/out}

//BEGIN POP INSTRUCTION ******************************************
//All POP variations are supported, except the useless repeats.
{pop}
reg32 = 0101 1 <regdest>|
reg16 = 0101 1 <regdest>|
mem = 1000 1111 : <mod> 000 <r/m>
{/pop}

//BEGIN PUSH INSTRUCTION ****************************************************
//All PUSH variations are supported, except the useless repeats.
{push}
reg32 = 0101 0 <regdest>|
reg16 = 0101 0 <regdest>|
mem = 1111 1111 : <mod> 110 <r/m>|
imm = 0110 10<s>0 : <imm>
{/push}

//BEGIN RCR INSTRUCTION *****************************************************
//(All variations supported)
{rcr}
reg,1 = 1101 000<w> : 11 011 <regdest>|
mem,1 = 1101 000<w> : <mod> 011 <r/m>|
reg,cl = 1101 001<w> : 11 011 <regdest>|
mem,cl = 1101 001<w> : <mod> 011 <r/m>|
reg,byte = 1100 000<w> : 11 011 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 011 <r/m> : <byte>
{/rcr}

//BEGIN RCL INSTRUCTION *****************************************************
//(All variations supported)
{rcl}
reg,1 = 1101 000<w> : 11 010 <regdest>|
mem,1 = 1101 000<w> : <mod> 010 <r/m>|
reg,cl = 1101 001<w> : 11 010 <regdest>|
mem,cl = 1101 001<w> : <mod> 010 <r/m>|
reg,byte = 1100 000<w> : 11 010 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 010 <r/m> : <byte>
{/rcl}

//BEGIN RETN INSTRUCTION *****************************************************
//(All variations supported)
{retn}
word = 1100 0010 : <word>
{/retn}

//BEGIN ROL INSTRUCTION *****************************************************
//(All variations supported)
{rol}
reg,1 = 1101 000<w> : 11 000 <regdest>|
mem,1 = 1101 000<w> : <mod> 000 <r/m>|
reg,cl = 1101 001<w> : 11 000 <regdest>|
mem,cl = 1101 001<w> : <mod> 000 <r/m>|
reg,byte = 1100 000<w> : 11 000 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 000 <r/m> : <byte>
{/rol}

//BEGIN ROR INSTRUCTION *****************************************************
//(All variations supported)
{ror}
reg,1 = 1101 000<w> : 11 001 <regdest>|
mem,1 = 1101 000<w> : <mod> 001 <r/m>|
reg,cl = 1101 001<w> : 11 001 <regdest>|
mem,cl = 1101 001<w> : <mod> 001 <r/m>|
reg,byte = 1100 000<w> : 11 001 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 001 <r/m> : <byte>
{/ror}

//BEGIN SAR INSTRUCTION *****************************************************
//(All variations supported)
{sar}
reg,1 = 1101 000<w> : 11 111 <regdest>|
mem,1 = 1101 000<w> : <mod> 111 <r/m>|
reg,cl = 1101 001<w> : 11 111 <regdest>|
mem,cl = 1101 001<w> : <mod> 111 <r/m>|
reg,byte = 1100 000<w> : 11 111 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 111 <r/m> : <byte>
{/sar}

//BEGIN SBB INSTRUCTION *****************************************************
//All SBB variations are supported, except the useless repeats.
{sbb}
//First entry is for optimization.
eax_ax_al,byte = 1000 00<s><w> : 11 011 000 : <byte>|
eax_ax_al,imm = 0001 110<w> : <imm>|
reg,imm = 1000 00<s><w> : 11 011 <regdest> : <imm>|

reg,reg = 0001 100<w> : 11 <regsrc> <regdest>|
reg,mem = 0001 101<w> : <mod> <regdest> <r/m>|
mem,reg = 0001 100<w> : <mod> <regsrc> <r/m>|

mem,imm = 1000 00<s><w> : <mod> 011 <r/m> : <imm>
{/sbb}

//BEGIN SGDT INSTRUCTION *****************************************************
//(All variations supported)
{sgdt}
mem = 0000 1111 : 0000 0001 : <mod> 000 <r/m>
{/sgdt}

//BEGIN SHL INSTRUCTION *****************************************************
//(All variations supported)
{shl}
reg,1 = 1101 000<w> : 11 100 <regdest>|
mem,1 = 1101 000<w> : <mod> 100 <r/m>|
reg,cl = 1101 001<w> : 11 100 <regdest>|
mem,cl = 1101 001<w> : <mod> 100 <r/m>|
reg,byte = 1100 000<w> : 11 100 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 100 <r/m> : <byte>
{/shl}

//BEGIN SHLD INSTRUCTION *****************************************************
//(All variations supported)
{shld}
reg,reg,byte = 0000 1111 : 1010 0100 : 11 <regsrc> <regdest> : <byte>|
mem,reg,byte = 0000 1111 : 1010 0100 : <mod> <regsrc> <r/m> : <byte>|
reg,reg,cl = 0000 1111 : 1010 0101 : 11 <regsrc> <regdest>|
mem,reg,cl = 0000 1111 : 1010 0101 : <mod> <regsrc> <r/m>
{/shld}

//BEGIN SHR INSTRUCTION *****************************************************
//(All variations supported)
{shr}
reg,1 = 1101 000<w> : 11 101 <regdest>|
mem,1 = 1101 000<w> : <mod> 101 <r/m>|
reg,cl = 1101 001<w> : 11 101 <regdest>|
mem,cl = 1101 001<w> : <mod> 101 <r/m>|
reg,byte = 1100 000<w> : 11 101 <regdest> : <byte>|
mem,byte = 1100 000<w> : <mod> 101 <r/m> : <byte>
{/shr}

//BEGIN SHRD INSTRUCTION *****************************************************
//(All variations supported)
{shrd}
reg,reg,byte = 0000 1111 : 1010 1100 : 11 <regsrc> <regdest> : <byte>|
mem,reg,byte = 0000 1111 : 1010 1100 : <mod> <regsrc> <r/m> : <byte>|
reg,reg,cl = 0000 1111 : 1010 1101 : 11 <regsrc> <regdest>|
mem,reg,cl = 0000 1111 : 1010 1101 : <mod> <regsrc> <r/m>
{/shrd}

//BEGIN SIDT INSTRUCTION *****************************************************
//(All variations supported)
{sidt}
mem = 0000 1111 : 0000 0001 : <mod> 001 <r/m>
{/sidt}

//BEGIN SLDT INSTRUCTION *****************************************************
//(All variations supported)
{sldt}
reg = 0000 1111 : 0000 0000 : 11 000 <regdest> |
mem = 0000 1111 : 0000 0000 : <mod> 000 <r/m>
{/sldt}

//BEGIN SMSW INSTRUCTION *****************************************************
//(All variations supported)
{smsw}
reg = 0000 1111 : 0000 0001 : 11 100 <regdest> |
mem = 0000 1111 : 0000 0001 : <mod> 100 <r/m>
{/smsw}

//BEGIN STR INSTRUCTION *****************************************************
//(All variations supported)
{str}
reg = 0000 1111 : 0000 0000 : 11 001 <regdest>|
mem = 0000 1111 : 0000 0000 : <mod> 001 <r/m>
{/str}

//BEGIN SUB INSTRUCTION *****************************************************
//All SUB variations are supported, except the useless repeats.
{sub}
//First entry is for optimization.
eax_ax_al,byte = 1000 00<s><w> : 11 101 000 : <byte>|
eax_ax_al,imm = 0010 110<w> : <imm>|
reg,imm = 1000 00<s><w> : 11 101 <regdest> : <imm>|

reg,reg = 0010 100<w> : 11 <regsrc> <regdest>|
reg,mem = 0010 101<w> : <mod> <regdest> <r/m>|
mem,reg = 0010 100<w> : <mod> <regsrc> <r/m>|

mem,imm = 1000 00<s><w> : <mod> 101 <r/m> : <imm>
{/sub}

//BEGIN TEST INSTRUCTION *****************************************************
//(All variations supported)
{test}
eax_ax_al,imm = 1010 100<w> : <imm>|
reg,reg = 1000 010<w> : 11 <regsrc><regdest>|
reg,mem = 1000 010<w> : <mod> <regdest> <r/m>|
reg,imm = 1111 011<w> : 11 000 <regdest> : <imm>|
mem,imm = 1111 011<w> : <mod> 000 <r/m> : <imm>
{/test}

//BEGIN VERR INSTRUCTION *****************************************************
//(All variations supported)
{verr}
reg16 = 0000 1111 : 0000 0000 : 11 100 <regdest>|
memword = 0000 1111 : 0000 0000 : <mod> 100 <r/m>
{/verr}

//BEGIN VERW INSTRUCTION *****************************************************
//(All variations supported)
{verw}
reg16 = 0000 1111 : 0000 0000 : 11 101 <regdest>|
memword = 0000 1111 : 0000 0000 : <mod> 101 <r/m>
{/verw}

//BEGIN XADD INSTRUCTION *****************************************************
//(All variations supported)
{xadd}
reg,reg = 0000 1111 : 1100 000<w> : 11 <regsrc> <regdest>|
mem,reg = 0000 1111 : 1100 000<w> : <mod> <regsrc> <r/m>
{/xadd}

//BEGIN XOR INSTRUCTION *****************************************************
//(All variations supported)
{xor}
eax_ax_al,imm = 0011 010<w> : <imm>|
reg,reg = 0011 000<w> : 11 <regsrc><regdest>|
reg,mem = 0011 001<w> : <mod> <regdest> <r/m>|
mem,reg = 0011 000<w> : <mod> <regsrc> <r/m>|
reg,imm = 1000 00<s><w> : 11 110 <regdest> : <imm>|
mem,imm = 1000 00<s><w> : <mod> 110 <r/m> : <imm>
{/xor}

//BEGIN XCHG INSTRUCTION *****************************************************
//(All variations supported)
{xchg}
reg8,al = 1000 0110 : 11 000<regdest>|
al,reg8 = 1000 0110 : 11 <regsrc>000|
reg,eax_ax_al = 1001 0 <regdest>|
//Note that for XCHG, the ordering of operands doesn't matter.
eax_ax_al,reg = 1001 0 <regsrc>|
reg,reg = 1000 011<w> : 11 <regsrc><regdest>|
reg,mem = 1000 011<w> : <mod> <regdest> <r/m>|
//Note that for XCHG, the ordering of operands doesn't matter.
mem,reg = 1000 011<w> : <mod> <regsrc> <r/m>|
{/xchg}

//SYSTEM COMMAND: print :label
{print}
imm = <dword>
{/print}

/*@~`!`~@@~`!`~@@~`!`~@@ BEGIN ALL JUMP INSTRUCTIONS @@~`!`~@@~`!`~@@~`!`~@@@*/
//BEGIN JMP INSTRUCTION **********************
{jmp}
reldisp8 = 1110 1011 : <reldisp8>|
reldisp = 1110 1001 : <reldisp>|
reg = 1111 1111 : 11 100 <regdest>|
mem = 1111 1111 : <mod> 100 <r/m>
{/jmp}

/*JUMP TEMPLATE:
{jxx}
reldisp8 = 0111 tttn : <reldisp8>|
reldisp = 0000 1111 : 1000 tttn : <reldisp>|
{/jxx}
*/
{je}
reldisp8 = 0111 0100 : <reldisp8>|
reldisp = 0000 1111 : 1000 0100 : <reldisp>
{/je}

{jne}
reldisp8 = 0111 0101 : <reldisp8>|
reldisp = 0000 1111 : 1000 0101 : <reldisp>
{/jne}

{jle}
reldisp8 = 0111 1110 : <reldisp8>|
reldisp = 0000 1111 : 1000 1110 : <reldisp>
{/jle}

{jge}
reldisp8 = 0111 1101 : <reldisp8>|
reldisp = 0000 1111 : 1000 1101 : <reldisp>
{/jge}

{jl}
reldisp8 = 0111 1100 : <reldisp8>|
reldisp = 0000 1111 : 1000 1100 : <reldisp>
{/jl}

{jg}
reldisp8 = 0111 1111 : <reldisp8>|
reldisp = 0000 1111 : 1000 1111 : <reldisp>
{/jg}

{js}
reldisp8 = 0111 1000 : <reldisp8>|
reldisp = 0000 1111 : 1000 1000 : <reldisp>
{/js}

{jo}
reldisp8 = 0111 0000 : <reldisp8>|
reldisp = 0000 1111 : 1000 0000 : <reldisp>
{/jo}

{jns}
reldisp8 = 0111 1001 : <reldisp8>|
reldisp = 0000 1111 : 1000 1001 : <reldisp>
{/jns}

{jno}
reldisp8 = 0111 0001 : <reldisp8>|
reldisp = 0000 1111 : 1000 0001 : <reldisp>
{/jno}

{jnp}
reldisp8 = 0111 1011 : <reldisp8>|
reldisp = 0000 1111 : 1000 1011 : <reldisp>
{/jnp}

{jp}
reldisp8 = 0111 1010 : <reldisp8>|
reldisp = 0000 1111 : 1000 1010 : <reldisp>
{/jp}

{ja}
reldisp8 = 0111 0111 : <reldisp8>|
reldisp = 0000 1111 : 1000 0111 : <reldisp>
{/ja}

{jb}
reldisp8 = 0111 0010 : <reldisp8>|
reldisp = 0000 1111 : 1000 0010 : <reldisp>
{/jb}

{jbe}
reldisp8 = 0111 0110 : <reldisp8>|
reldisp = 0000 1111 : 1000 0110 : <reldisp>
{/jbe}

{jnb}
reldisp8 = 0111 0011 : <reldisp8>|
reldisp = 0000 1111 : 1000 0011 : <reldisp>
{/jnb}
/*@~`!`~@@~`!`~@@~`!`~@@ END ALL JUMP INSTRUCTIONS @@~`!`~@@~`!`~@@~`!`~@@@*/

/*@~`!`~@@~`!`~@@~`!`~@@ BEGIN ALL CMOV INSTRUCTIONS @@~`!`~@@~`!`~@@~`!`~@@@*/
{cmovo}
reg32,reg32 = 0000 1111: 0100 0000 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0000 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0000 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0000 : <mod> <regdest> <r/m>
{/cmovo}

{cmovno}
reg32,reg32 = 0000 1111: 0100 0001 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0001 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0001 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0001 : <mod> <regdest> <r/m>
{/cmovno}

{cmovb}
reg32,reg32 = 0000 1111: 0100 0010 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0010 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0010 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0010 : <mod> <regdest> <r/m>
{/cmovb}

{cmovnb}
reg32,reg32 = 0000 1111: 0100 0011 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0011 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0011 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0011 : <mod> <regdest> <r/m>
{/cmovnb}

{cmove}
reg32,reg32 = 0000 1111: 0100 0100 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0100 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0100 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0100 : <mod> <regdest> <r/m>
{/cmove}

{cmovne}
reg32,reg32 = 0000 1111: 0100 0101 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0101 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0101 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0101 : <mod> <regdest> <r/m>
{/cmovne}

{cmovbe}
reg32,reg32 = 0000 1111: 0100 0110 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0110 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0110 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0110 : <mod> <regdest> <r/m>
{/cmovbe}

{cmova}
reg32,reg32 = 0000 1111: 0100 0111 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 0111 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 0111 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 0111 : <mod> <regdest> <r/m>
{/cmova}

{cmovs}
reg32,reg32 = 0000 1111: 0100 1000 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1000 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1000 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1000 : <mod> <regdest> <r/m>
{/cmovs}

{cmovns}
reg32,reg32 = 0000 1111: 0100 1001 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1001 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1001 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1001 : <mod> <regdest> <r/m>
{/cmovns}

{cmovp}
reg32,reg32 = 0000 1111: 0100 1010 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1010 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1010 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1010 : <mod> <regdest> <r/m>
{/cmovp}

{cmovnp}
reg32,reg32 = 0000 1111: 0100 1011 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1011 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1011 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1011 : <mod> <regdest> <r/m>
{/cmovnp}

{cmovl}
reg32,reg32 = 0000 1111: 0100 1100 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1100 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1100 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1100 : <mod> <regdest> <r/m>
{/cmovl}

{cmovge}
reg32,reg32 = 0000 1111: 0100 1101 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1101 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1101 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1101 : <mod> <regdest> <r/m>
{/cmovge}

{cmovle}
reg32,reg32 = 0000 1111: 0100 1110 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1110 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1110 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1110 : <mod> <regdest> <r/m>
{/cmovle}

{cmovg}
reg32,reg32 = 0000 1111: 0100 1111 : 11 <regdest> <regsrc>|
reg16,reg16 = 0000 1111: 0100 1111 : 11 <regdest> <regsrc>|
reg32,mem = 0000 1111: 0100 1111 : <mod> <regdest> <r/m>|
reg16,memword = 0000 1111: 0100 1111 : <mod> <regdest> <r/m>
{/cmovg}
/*@~`!`~@@~`!`~@@~`!`~@@ END ALL CMOV INSTRUCTIONS @@~`!`~@@~`!`~@@~`!`~@@@*/

/*@~`!`~@@~`!`~@@~`!`~@@ BEGIN ALL SET INSTRUCTIONS @@~`!`~@@~`!`~@@~`!`~@@@*/
{seto}
reg8 = 0000 1111 : 1001 0000 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0000 : <mod> 000 <r/m>
{/seto}

{setno}
reg8 = 0000 1111 : 1001 0001 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0001 : <mod> 000 <r/m>
{/setno}

{setb}
reg8 = 0000 1111 : 1001 0010 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0010 : <mod> 000 <r/m>
{/setb}

{setnb}
reg8 = 0000 1111 : 1001 0011 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0011 : <mod> 000 <r/m>
{/setnb}

{sete}
reg8 = 0000 1111 : 1001 0100 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0100 : <mod> 000 <r/m>
{/sete}

{setne}
reg8 = 0000 1111 : 1001 0101 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0101 : <mod> 000 <r/m>
{/setne}

{setbe}
reg8 = 0000 1111 : 1001 0110 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0110 : <mod> 000 <r/m>
{/setbe}

{seta}
reg8 = 0000 1111 : 1001 0111 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 0111 : <mod> 000 <r/m>
{/seta}

{sets}
reg8 = 0000 1111 : 1001 1000 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1000 : <mod> 000 <r/m>
{/sets}

{setns}
reg8 = 0000 1111 : 1001 1001 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1001 : <mod> 000 <r/m>
{/setns}

{setp}
reg8 = 0000 1111 : 1001 1010 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1010 : <mod> 000 <r/m>
{/setp}

{setnp}
reg8 = 0000 1111 : 1001 1011 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1011 : <mod> 000 <r/m>
{/setnp}

{setl}
reg8 = 0000 1111 : 1001 1100 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1100 : <mod> 000 <r/m>
{/setl}

{setge}
reg8 = 0000 1111 : 1001 1101 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1101 : <mod> 000 <r/m>
{/setge}

{setle}
reg8 = 0000 1111 : 1001 1110 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1110 : <mod> 000 <r/m>
{/setle}

{setg}
reg8 = 0000 1111 : 1001 1111 : 11 000 <regdest>|
membyte = 0000 1111 : 1001 1111 : <mod> 000 <r/m>
{/setg}
/*@~`!`~@@~`!`~@@~`!`~@@ END ALL SET INSTRUCTIONS @@~`!`~@@~`!`~@@~`!`~@@@*/

/* NOTE: in the intel PDF, they have a funky way of ordering their operands.
They do it the right way! (gasp!)

CMP
reg1 with reg2  --Actually means CMP reg2,reg1

MOV
memory to reg   --Actually means MOV reg,[memory]

So just always reverse them (except with IMUL). And test with OllyDbg when in doubt!
*/

/* If you add instructions to this list, make sure you add the same
instructions to the "supported instructions" method for the Assembler itself!*/